Raised Challenges by NVRAM

New memory technologies impact various fields of computer science but it is hard to evaluate, as specialists of one scientific domain, what are these fields and how important is this impact. In this talk, I will present this problematics and I'll introduce the various themes that we will talk about during the workshop. Also, I'll give some examples of existing works that let me think that emerging memories will lead to new usages in computer science, and not only to minor optimisations of some domains. Bio : Kevin Marquet is an associate professor at the Computer Science and Information Technology department of INSA-Lyon, and a member of the CITI laboratory since 2010. He holds a PhD (2007) and a MSc (2004) both from Université Lille 1 where he studied automatic dynamic memory management for embedded Java applications. Before joining the CITI lab, he was a post-doctoral researcher at the Verimag lab in Grenoble, France where he worked on embedded systems verification. His research interests lie in the area of compilation and operating system support for embedded systems, with a focus on memory management. 14:00 From Embedded World to High Performance Computing using STT-MRAM Lionel Torres LIRRM Abstract : The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This talk shows first how STT-MRAM can improve energy efficiency and reliability of future systems (HPC & Embedded Systems). We will present the potential of STT-MRAM to design non-volatile processor with two interesting capabilities for energy-efficient and reliable embedded systems: instant-on/off and rollback. We will also discuss about a hybrid design exploration flow to investigate the overall performance impact of using STT-MRAM into the memory hierarchy of HPC systems. Bio : Lionel Torres obtained respectively my Master and PhD degree in 1993 and 1996 from the University of Montpellier. From 1996 to 1997 he was in ATMEL company as IP core methodology R&D engineer. From 1997 to 2004 he was assistant professor at the University of Montpellier, Polytech'Montpellier (Microelectronic design) and LIRMM laboratory. Since 2004 he is full Professor and was at the head of the Microelectronic dpt of the LIRMM from 2007 to 2010. I am now deputy head of Polytech'Montpellier (engineering school of Montpellier) in charge of research, industrial and international relationship. He is at the Head of the Labex NUMEV (Laboratory of Excellence on digital hardware solutions, Environmental and Organic Life Modeling). His research interests and skills concern system level architecture, with a specific focus on Non-Volatile Computing based on emerging technologies, especially MRAM. He leads several European, national and industrial projects in this field. He is involved in different major conference as DATE, VLSI, FPL, ISVLSI, DAC and is (co)author of more than 40 journal papers and 150 conference publications and 7 patents The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This talk shows first how STT-MRAM can improve energy efficiency and reliability of future systems (HPC & Embedded Systems). We will present the potential of STT-MRAM to design non-volatile processor with two interesting capabilities for energy-efficient and reliable embedded systems: instant-on/off and rollback. We will also discuss about a hybrid design exploration flow to investigate the overall performance impact of using STT-MRAM into the memory hierarchy of HPC systems. Bio : Lionel Torres obtained respectively my Master and PhD degree in 1993 and 1996 from the University of Montpellier. From 1996 to 1997 he was in ATMEL company as IP core methodology R&D engineer. From 1997 to 2004 he was assistant professor at the University of Montpellier, Polytech'Montpellier (Microelectronic design) and LIRMM laboratory. Since 2004 he is full Professor and was at the head of the Microelectronic dpt of the LIRMM from 2007 to 2010. I am now deputy head of Polytech'Montpellier (engineering school of Montpellier) in charge of research, industrial and international relationship. He is at the Head of the Labex NUMEV (Laboratory of Excellence on digital hardware solutions, Environmental and Organic Life Modeling). His research interests and skills concern system level architecture, with a specific focus on Non-Volatile Computing based on emerging technologies, especially MRAM. He leads several European, national and industrial projects in this field. He is involved in different major conference as DATE, VLSI, FPL, ISVLSI, DAC and is (co)author of more than 40 journal papers and 150 conference publications and 7 patents 14:45 Maximize energy efficiency in normally-off system using NVRAM Stéphane Gros and Yeter Akgul Evaderis Abstract : Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting the processing performances. One of the solutions is to rely on Non-Volatile Memories (NVM) and their integration within complex systems. This presentation will show how to benefit from NVRAM technologies and overcome their limitations into a Normally-Off architecture. Bio : • Stéphane Gros, System Architect: Stéphane has 5 years of experience in digital design. He started Energy efficient computing has become the key to enable the portability of new applications onto mobile devices which need to be always smaller and more powerful. As the technology node shrinks, the leakage current increases exponentially in deep submicron CMOS, so that new strategies are required in integrated systems to save power without limiting the processing performances. One of the solutions is to rely on Non-Volatile Memories (NVM) and their integration within complex systems. This presentation will show how to benefit from NVRAM technologies and overcome their limitations into a Normally-Off architecture. Bio : • Stéphane Gros, System Architect: Stéphane has 5 years of experience in digital design. He started his career at Sigma Designs (USA), and then joined the team, at the CEA (France), who later founded eVaderis. Finally, Stéphane was one of the first employee at the creation of the start-up. He oversees the definition of the system architecture, its implementation, verification and benchmark. • Yeter Akgul, Memory Design Engineer: Yeter holds a PhD from the University of Montpellier (France) on “Power Management based on Dynamic Voltage, Frequency and Body Bias Scaling on System on Chip in FD-SOI technology” supervised by the CEA-LETI in collaboration with the LIRMM. She started memory design, SRAM and MRAM, at Tohoku University (Japan), the leader laboratory on MRAM. Finally, she was hired at eVaderis as a memory and NV-logic designer."